Open Access
Peer-Reviewed
Foundational Models & Architectures
Vhdl Design for a Speed Limit Sign Segmentation Algorithm
Abstract
One of the most important and challengi ng tasks in the image processing field is color segmentation . In this paper, we propose a red color segmentation algorithm which is developed to be used as a mandatory task of a complete vision based intelligent speed limit road sign recognition system. This type of sign is characterized by a red border. For this reason the segmentation remains important in the detection task. A simple and accurate technique was proposed which presents a modified and improved thresholding based method that uses the Red, Green and Blue color space components . In order to improve the robustness and efficiency, a pretreatment was proposed in our work to be applied on images before thresholding. This pretreatment is divided into two steps; the first one is c lassification. The ai m is to classify images according to different illumination condition s. The second one consists in color adjustment and correction. These two algorithms were introduced to solve problems caused firstly by the use of same thresholding values for different i mages, and secondly by the sensibility of colors to lightening conditions variation. The comparison with existent methods has shown robustness and accuracy mainly for images of different day times and for faded and blurred signs . In addition to that low c omputation time is achieved. The software implementation of the developed segmentation algorithm using MATLAB tool is discussed in this paper, as well as the simulation results of the VHDL Circuit using ModelSim tool. Computational time reduction, low complexity and low resource utilization have shown the effectiveness of our approach.
Keywords
Image processing
Color segmentation
Color spaces
VHDL implementation
Declarations & Ethics
Funding:
This research received academic dissemination support through ESCAP / JournalsHub publishing programs.
Conflicts of Interest:
The authors declare no competing financial or institutional interests.
Peer Review:
Double-blind peer reviewed by international subject specialists.
License:
Creative Commons Attribution 4.0 International (CC BY 4.0).
How to Cite This Article
APA / MLA / BibTeX
Rouabeh, et al. (2017). Vhdl Design for a Speed Limit Sign Segmentation Algorithm. IADIS International Journal on Computer Science and Information Systems, 12(2). https://doi.org/10.33965/ijcsis_2017_v12i2_04
Rouabeh, et al. "Vhdl Design for a Speed Limit Sign Segmentation Algorithm." IADIS International Journal on Computer Science and Information Systems, vol. 12, no. 2, 2017. https://doi.org/10.33965/ijcsis_2017_v12i2_04
Rouabeh, et al. "Vhdl Design for a Speed Limit Sign Segmentation Algorithm." IADIS International Journal on Computer Science and Information Systems 12, no. 2 (2017). https://doi.org/10.33965/ijcsis_2017_v12i2_04